[alsa-devel] [PATCH 2/2] ASoC: tlv320aic3x: Clear BIT_CLK_MASTER and WORD_CLK_MASTER bits for for slave mode

[Jarkko Nikula]

On Thu, 2011-10-27 at 16:38 +0800, Axel Lin wrote:
> According to the datasheet:
> 
> Page0 / Register8: Audio Serial Data interface Control Register A
> BIT 7: Bit Clock Directional Control
>         0: Bit clock is an input (slave mode)
>         1: Bit clock is an output (master mode)
> 
> BIT 6: Word Clock Directional Control
>         0: Word clock is an input (slave mode)
>         1: Word clock is an output (master mode)
> 
> Current code sets BIT_CLK_MASTER and WORD_CLK_MASTER bits for master mode,
> but does not clear these bits for slave mode.
> 
> Signed-off-by: Axel Lin <axel.lin at gmail.com>
> ---
>  sound/soc/codecs/tlv320aic3x.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
This is not entirely true - there is this fussy '& 0x3f' operation that
does clear those bits a few code lines above your change. Now we can rid
of it thanks to your patch, hopefully for iface_breg too (in case if you
are going to send an another patch as this is applied) :-)

-- 
Jarkko