[alsa-devel] [PATCH 1/2 v2] ASoC: soc-cache: block based rbtree compression
broonie at opensource.wolfsonmicro.com
Tue May 3 17:48:47 CEST 2011
On Tue, May 03, 2011 at 05:47:07PM +0200, Takashi Iwai wrote:
> IMO, it's easier to expose an API that allows the update of an
> register array. The rest is a job of the cache backend stuff.
> As a fallback, it can be a loop of the single read/write.
We'll want to do that as well, but we still want the actual data
structure underneath to support that. Since most register maps that
benefit from compression are also sparse rbtree is the common case for
getting a win from this.
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