[alsa-devel] [PATCH 1/2 v2] ASoC: soc-cache: block based rbtree compression
tiwai at suse.de
Tue May 3 16:07:42 CEST 2011
At Tue, 3 May 2011 14:51:28 +0100,
Mark Brown wrote:
> On Tue, May 03, 2011 at 03:32:47PM +0200, Takashi Iwai wrote:
> > Hrm, then I don't understand why changing the cache management changes
> > the bulk I/O behavior as you described. What's missing there?
> If we can't get the data laid out in a contiguous array in memory then
> we have to gather the data for transmit in the I/O code which is
> painful and wasteful.
But it's just a matter of CPU usage to look for the caches.
Well, what I don't understand is the text you wrote:
| > So... when the low-level stuff updates the registers in a block
| > manner, it'll update caches of several registers at once, too.
| > If I understand correctly, the patches help for reducing the CPU usage
| > because the registers looked up in such a case tend to be adjacent.
| > Or am I missing other scenario?
| This isn't about CPU usage, it's about I/O bandwidth which is a big
| concern in situations like resume where you can be bringing the device
| back up from cold.
How does the contiguous memory layout inside the cache management
reduce the I/O bandwidth...?
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