[alsa-devel] Creative X-Fi Titanium HD ctxfi bugs 5378 5218 4868

[Takashi Iwai]

At Thu, 16 Jun 2011 08:32:15 +0800,
Harry Butterworth wrote:
> 
> On 14 June 2011 16:23, Harry Butterworth <heb1001 at gmail.com> wrote:
> > Great.  Creative got back to me today with a proposed solution for the
> > PLL initialization.  I'll follow up with another patch in the next
> > week probably.
> 
> Here's the change from Creative for the PLL initialization.  It works
> for me and hasn't failed yet but it didn't fail that often before and
> I don't have the chip spec so I can't vouch for the new magic numbers.

Thanks, I applied it now.  Let's see whether this breaks others.


Takashi

> 
> Harry
> [2 0003-ALSA-ctxfi-Change-PLL-initialization-code.patch <text/x-patch; US-ASCII (base64)>]
> From 27b2ddf7343d569764da750d39dd403d1648cf06 Mon Sep 17 00:00:00 2001
> From: Harry Butterworth <heb1001 at gmail.com>
> Date: Tue, 14 Jun 2011 23:09:12 +0800
> Subject: [PATCH - ALSA:ctxfi 3/3] ALSA: ctxfi: Change PLL initialization code
> 
> This is a reworked patch from Creative to change the PLL code to address
> unreliable 44100Hz initialization.
> 
> Signed-off-by: Harry Butterworth <heb1001 at gmail.com>
> 
> diff --git a/pci/ctxfi/cthw20k2.c b/pci/ctxfi/cthw20k2.c
> index ea559a9..4101a8e 100644
> --- a/pci/ctxfi/cthw20k2.c
> +++ b/pci/ctxfi/cthw20k2.c
> @@ -1316,21 +1316,18 @@ static int hw_pll_init(struct hw *hw, unsigned int rsr)
>  
>  	pllenb = 0xB;
>  	hw_write_20kx(hw, PLL_ENB, pllenb);
> -	pllctl = 0x20D00000;
> -	set_field(&pllctl, PLLCTL_FD, 16 - 4);
> +	pllctl = 0x20C00000;
> +	set_field(&pllctl, PLLCTL_B, 0);
> +	set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4);
> +	set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1);
>  	hw_write_20kx(hw, PLL_CTL, pllctl);
>  	mdelay(40);
> +
>  	pllctl = hw_read_20kx(hw, PLL_CTL);
> -	set_field(&pllctl, PLLCTL_B, 0);
> -	if (48000 == rsr) {
> -		set_field(&pllctl, PLLCTL_FD, 16 - 2);
> -		set_field(&pllctl, PLLCTL_RD, 1 - 1); /* 3000*16/1 = 48000 */
> -	} else { /* 44100 */
> -		set_field(&pllctl, PLLCTL_FD, 147 - 2);
> -		set_field(&pllctl, PLLCTL_RD, 10 - 1); /* 3000*147/10 = 44100 */
> -	}
> +	set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2);
>  	hw_write_20kx(hw, PLL_CTL, pllctl);
>  	mdelay(40);
> +
>  	for (i = 0; i < 1000; i++) {
>  		pllstat = hw_read_20kx(hw, PLL_STAT);
>  		if (get_field(pllstat, PLLSTAT_PD))
> -- 
> 1.7.0.4
>