[alsa-devel] soc-dsp questions
lrg at ti.com
Mon Jun 13 19:55:00 CEST 2011
On 11/06/11 12:48, Mark Brown wrote:
> On Fri, Jun 10, 2011 at 06:19:57PM -0700, Patrick Lai wrote:
>> Another query I have is how to handle back-end error. The audio bus
>> which is running on my machine requires close coordination between CPU
>> and CODEC. Essentially, if one side is unable to respond to incoming
>> data in time, data exchange halts. I am looking for way to reset both
>> CPU and CODEC back to fresh state. One approach I am thinking is to
>> generate XRUN error(snd_pcm_stop(SNDRV_PCM_STATE_XRUN) and have
>> application call prepare() to reset CPU and CODEC back to good state.
>> I see each back-end is registered as PCM device so it's possible that
>> application can read /dev/snd/timer to get notified. However, do I call
>> prepare() on one of FE PCM devices that are routed to the back end in
>> question? Would this approach work? Any suggestion?
> I'd expect that from an application point of view this will just work
> already? The application will just operate on the PCM it's operating on
> and will notice a stall in the same way it does for any other device
> then the front/back end machinery will connect everything up in the same
> way it does for every operation when (if!) the application tries to
This is how it works on OMAP4.
The ABE handles and recovers most BE errors internally and can also interrupt the CPU for serious errors (to signal XRUNs etc).
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