[alsa-devel] snd soc spi read/write

Scott Jiang scott.jiang.linux at gmail.com
Fri Aug 5 10:00:52 CEST 2011

> Why are you replying off-list?  You should implement 16x8 SPI reads in
> the core stuff I'd expect, then disable cache for the CODEC.

Sorry, I just forgot to CC.
I wonder if rbtree compress type can support this kind of sparse register?
And should the patch aginst 3.0 or 3.2?

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