[alsa-devel] [PATCH RESEND] ASoC: sgtl5000: fix cache handling
lrg at ti.com
Tue Aug 2 22:11:44 CEST 2011
On 02/08/11 18:42, Wolfram Sang wrote:
> Cache handling in this driver is broken. The chip has 16-bit registers, yet the
> register numbers also increase by 2 per register, i.e. there are only
> even-numbered registers. The cache in this driver, though, simply increments
> register numbers, so it does need some mapping as seen in
> sgtl5000_restore_regs(), note the '>> 1':
> snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
> cache[SGTL5000_CHIP_LINREG_CTRL >> 1]);
> That, of course, won't work with snd_soc_update_bits(). (Thus, we won't even
> notice the missing register 0x1c in the default regs which shifted all follwing
> registers to wrong values.) Noticed on the MX28EVK where enabling the regulators
> simply locked up the chip.
> Refactor the routines and use a properly sized default_regs array which matches
> the register layout of the underlying chip, i.e. create a truly flat cache.
> This also saves some code which should make up for the bigger array a little.
> When soc-core will somewhen have another cache type which handles a step size,
> this conversion will also ease the transition.
This would probably be the preferred solution. I guess we can wait a little longer for this fix.
> Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
> Tested-by: Dong Aisheng <b29396 at freescale.com>
> Tested-by: Shawn Guo <shawn.guo at linaro.org>
> Cc: Zeng Zhaoming <b32542 at freescale.com>
> Cc: Liam Girdwood <lrg at ti.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg at ti.com>
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