[alsa-devel] USB asynchronous mode feedback format
daniel at caiaq.de
Thu Oct 14 14:06:41 CEST 2010
On Thu, Oct 14, 2010 at 01:32:37PM +0200, Julian Scheel wrote:
> Am Donnerstag, 14. Oktober 2010, 13:16:12 schrieb Daniel Mack:
> > The dump doesn't show whether the LRCLK is symmetrical, iow, whether the
> > low phase of LRCLK has the same number of BCLK cycles as the high phase.
> > But if that's the case, the signals do indeed look alright. Maybe you
> > need the configure the codec to this format?
> LRCLK is symmetrical. I use the modules from twistedpearaudio
> http://www.twistedpearaudio.com/digital/cod.aspx) because this saved me some
> time designing a PCB for now...
> They are configured through DIP switches - and I think correctly. For the SRC
> the settings are:
> OWL0,1,2: 0, 0, 0
> OFMT0,1: 1, 0
> MODE0,1,2: 1, 0, 0
> IFMT0,1,2: 1, 0, 0
> BYPASS: 0
> LGRP: 0
> What I am actually wondering about is, that the SRC produces some output even
> when the input is null. Attached is a picture of this case. I did not measure
> the BCLK this time.
Yes, that looks suspicious, especially because it doesn't only affect
the lower bits. What do you need this sample rate converter for, anyway?
Can't you feed your signals directly to the DAC? FMT0 and FMT1 should
both be set to 0.
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