[alsa-devel] [PATCH] S3C64XX I2S: Added machine driver for WM8580

jassi brar jassisinghbrar at gmail.com
Thu Sep 17 15:36:10 CEST 2009

On Thu, Sep 17, 2009 at 10:11 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Thu, Sep 17, 2009 at 09:26:28PM +0900, jassi brar wrote:
>> > > +       /* Currently, WM8580 driver doesn't support PLL-out rates
>> > > +        * other than those mentioned in Table-52 Page-58 of WM8580A
>> That very manual. And i don't say the WM8580 doesn't support, I said
>> the WM8580 driver doesn't support: which can be verified looking at the
>> CODEC driver.
> Your comment says that only the output frequencies in table 52 are
> supported.  Could you please provide more specific references to where
> this is done in the driver?  I think you're confusing the fact that the
> example table lists most of the common audio frequencies with what the
> driver supports here.
Let me be precise.
With this machine driver and the WM8580 CODEC driver from origin/for-2.6.32
if we do any of the following:-
   snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 12000000, 8000*256);
   snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 12000000, 11025*256);
   snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 12000000, 64000*256);
we get the error: "wm8580: Unable to scale output frequency"

>> Theoretically all output clocks are possible but usually the PLL coefficients
>> have limits on their value and thus final output. WM8580 driver too seems
>> to enforce that.
>> Though, you wud know better of WM8580.
> So what you're actually saying is that 256fs doesn't give us the option
> of an an in-range Fvco for the FLL at those frequencies (which is the
> check I think you're talking about here)?  That's a limitation of the
> chip.
> Certainly, the comment is not accurate - the contents of table 52 aren't
> relevant here, the driver is calculating what it can do dynamically so
> the restrictions are a combination of the limits on Fvco and the pre and
> post scaling dividers available.
Of course, there just might be a set of values for PLL coeffs that output
256fs for 8000, 11025 and 64000. If that set is within acceptable range of
of the chip then it's just a matter of driver upgrade otherwise its a
of the chip.
You wud know which case is it.

I apologize if my inappropriate selection of expression bothered you.
In future, please feel free to suggest modification of any comment in the
code. Regards.

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