[alsa-devel] Output frequency configuration for I2S in beagleboard? (underrun problem)

Ernesto Torres skullmate at gmail.com
Wed May 13 01:28:58 CEST 2009


Hi,

I would like to know the actual configuration for the output of the Beagle
Board I2S, from the OMAP35x Reference Manual, on page 2887:

• Enable the Sample Rate Generator (take it out of reset).
  Set McBSPi.MCBSPLP_SPCR2_REG[6] GRSTbit to1 to enable the Sample Rate
Generator.
  After the Sample Rate Generator is enabled, wait for 2 CLKG cycles for the
Sample Rate Generator
  logic to stabilize.
*  On the next rising edge of CLKSRG, the CLKG signal transitions to '1' and
starts clocking with a
  frequency equal to (input clock frequency)/(CLKGDV + 1).*
• If necessary, enable the receiver and/or the transmitter.

It says the clocking will start with the frequency of input clock (I thougth
it is 26Mhz but i've been told is 96Khz, not quite sure) and CLKGDV is a
variable number to get a desired frequency.

from omap-mcbsp.c:

*static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
                     int div_id, int div)
{
    struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
    struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
    dbg("omap_mcbsp_dai_set_clkdiv START");
    if (div_id != OMAP_MCBSP_CLKGDV)
        return -ENODEV;
    dbg("div: %d",div);
    regs->srgr1    |= CLKGDV(div - 1);
                dbg("omap_mcbsp_dai_set_clkdiv END");
    return 0;
}*

Here, the value is asigned to srgr1. I capture all actions from startup and
from aplay but this function is never called. Do you know when it should be
called or where we can find the div value?

I'm having trouble adapting an external codec from the beagle, and I think
it may be because of the output frequency from the beagle. I'm getting some
underruns during playback(with aplay) and I don't know exactly where to
begin.  Suggestions are welcome.

Thanks for your help

Best regards,
Ernesto


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