[alsa-devel] [PATCH 1/4] ASoC: Use network mode with 2 slots for 16-bit stereo in pxa-ssp/Zylonite

pHilipp Zabel philipp.zabel at gmail.com
Wed Mar 4 21:45:33 CET 2009

On Wed, Mar 4, 2009 at 2:34 AM, Daniel Mack <daniel at caiaq.de> wrote:
> Hi Phillip,
> glad to see someone is wasting time with that issue, too :)
> On Tue, Mar 03, 2009 at 04:10:51PM +0100, Philipp Zabel wrote:
>> For consistency with 24-bit and 32-bit modes, don't send 16-bit stereo
>> in one 32-bit transfer. Use 2 slots instead on Zylonite. It should result
>> in exactly the same behaviour.
>> Now it is possible to use 16-bit single slot transfers in pxa-ssp, which
>> are needed for Magician to get two frame clock pulses per sample
>> (one for each channel).
> We've been fiddling around with these modes and registers for
> another two days in a row now and figured out that literally all the
> documentation about these registers is entirly bogus. In particular,
> the network mode with the associated timeslots simply does not work at
> all, according to our measurements.
> Hence the question: how does your I2S signal look like at the moment?
> How many clocks do you measure in one frame cylce, how many of them are
> actually filled with data? And which format does the userspace use to
> send samples in?

Unfortunately, I can't measure anything. I don't own an oscilloscope
and I don't even know if there are useful test points on the phone's
Also, I've come to the conclusion that on Magician there has to be
some kind of flip-flop between the PXA272's SSPFRMCLK and the codec's
LRCLK input. I'm not using I2S mode at all, but TISSP (or PSP with
DAIFMT_DSP_A) and two full frames per sample.
I can more or less handle S16_LE and S32_LE from userspace now.
Using S24_LE doesn't work because the codec supports LSB aligned
signals only up to 20-bit.
S24_3LE I didn't try yet, but the PXA DMA can't advance the source
pointer by 3 bytes per transfer, so that would be ugly anyway (and
only possible if network mode works).

> We finally got a mode now that outputs 2x16 bit on a 2x32 bits I2S
> frame, padded with zeros. But that is in non-network modes, more
> about that tomorrow ...

Strange, interesting ...


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