[alsa-devel] [PATCH 1/4] ASoC: pxa-ssp: enhance I2S and add Left_J support

pHilipp Zabel philipp.zabel at gmail.com
Tue Jun 9 13:40:43 CEST 2009


On Tue, Jun 9, 2009 at 11:58 AM, Mark
Brown<broonie at opensource.wolfsonmicro.com> wrote:
> On Tue, Jun 09, 2009 at 05:39:18PM +0800, Eric Miao wrote:
>
>> OK, not having enough time to read all this thread, let's make sure
>> first we are on the same floor:
>
>> frame_width  = number of bit clocks per frame
>> sample_width = number of bits per sample
>
> Yes.
>
>> And the assumption that
>
>> frame_width = sample_width * channel ( = LRCLK for I2S )
>
>> is no longer (and ever) correct.
>
> Ish.  That's always been a minimum for most frame formats, though with
> programmable ports like the PXA SSP ports I2S normally makes it an exact
> requirement.  At the minute the magician is abusing a low frame width to
> produce a double rate frame clock but this is an abuse.
>
>> And the TDM mode is actually special for PXA-SSP to emulate the I2S
>> protocol, it's no way generic TDM in a common sense. So talking about
>> set_tdm_slots(), I'd really like to hide into the format setting code
>> of I2S/Left_J to avoid further confusion.
>
> In terms of the ASoC APIs TDM mode should only be required in order to
> configure actual TDM.  Ideally the PXA driver should only ever require
> set_tdm_slot() for actual TDM configurations and setting up a single
> slot for TDM should be equivalent to never having called it at all.
>
> It's use in the PXA code has always been a wart.
>
>> And I still didn't quite capture the issue of magician. Phillip, do
>> you have any HW reference to the audio codec and the connection on
>> magician?
>
> Essentially his hardware ends up requiring one frame clock per sample in
> a stereo stream - ie, a double rate frame clock.  I strongly expect that
> it is actually running in a DSP mode with one frame sync per sample
> rather than per frame.

Correct. A flip-flop between the PXA frame clock output and the
UDA1380 codec's LRCLK input turns the double rate DSP mode pulses into
an I2S style LRCLK signal.

I don't have any references for this, but the behaviour is consistent
(for example L/R channels are switched if I restart playback after
sending an odd number of samples without powering down first) and
suitable flip-flops appear in the HTC Blueangel list of parts at
http://www2.electronicproducts.com/HTC_XDA_III_Pocket_PC_Phone_-whatsinside-42.aspx.

regards
Philipp


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