[alsa-devel] [PATCH 1/4] ASoC: pxa-ssp: enhance I2S and add Left_J support

[Paul Shen]

Hi Daniel,

This is Paul Shen , I will substitute boshen9 at gmail.com  for
bshen9 at marvell.com to answer open source mails.


> From: Daniel Mack <daniel at caiaq.de>
> Date: Wed, Jun 3, 2009 at 9:18 PM
> Subject: Re: [alsa-devel] [PATCH 1/4] ASoC: pxa-ssp: enhance I2S and add Left_J support
> To: Eric Miao <eric.y.miao at gmail.com>
> Cc: alsa-devel at alsa-project.org, linux-arm-kernel <linux-arm-kernel at lists.arm.linux.org.uk>, Mark Brown <broonie at sirena.org.uk>
>
>
> On Wed, Jun 03, 2009 at 08:33:42PM +0800, Eric Miao wrote:
> > Make the pxa I2S configuration generic, add support for Left_J, add
> > support for variable frame width like 32fs, 48fs, 64fs and 96fs
> >
> > Signed-off-by: Paul Shen <bshen9 at marvell.com>
> > Signed-off-by: Eric Miao <eric.miao at marvell.com>
> > Cc: Daniel Mack <daniel at caiaq.de>
> > ---
> >  arch/arm/mach-pxa/include/mach/regs-ssp.h |   14 +++---
> >  sound/soc/pxa/pxa-ssp.c                   |   62 ++++++++++++++--------------
> >  sound/soc/pxa/pxa-ssp.h                   |    9 ++++
> >  3 files changed, 47 insertions(+), 38 deletions(-)
>
> Ok, I tried that code on my board and this is what I had to change
> there:
>
> The tdm time slot configuration needs to be set again in my board support
> code just like in your example: snd_soc_set_tdm_slot(cpu_dai, 3, 2). And
> the PXA_SSP_DIV_SCR value needed to be doubled from 4 to 8.
>
I tested  with below  codes to set the cpu_dai  :

format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
                         SND_SOC_DAIFMT_CBS_CFS | PXA_SSP_FRM_64FS;

snd_soc_dai_set_fmt(cpu_dai, format);
snd_soc_dai_set_tdm_slot(cpu_dai, 3, 2);

snd_soc_dai_set_sysclk(cpu_dai, PXA_SSP_CLK_EXT, clk, 0);
snd_soc_dai_set_clkdiv(cpu_dai, PXA_SSP_DIV_SCR, 4);

It is no need to "snd_soc_dai_set_pll(cpu_dai, 0, 0, clk)" , for  your
case ,no ssp-on-chip pll configuration is needed.

On my littleton platform,it is ok, and  I did not modify the
PXA_SSP_DIV_SCR from 4 to 8.

I dumped the ssp register:
SSCR0 0xa10003ff
SSCR1 0x00e01d80
SSTO 0x00000000
SSPSP 0x31a00084
SSSR 0x0000f0fc
SSACD 0x00000000
SSACDD 0x00000000

How about your registers ?

> With that changes, LRCLK is 44100Hz when configured to 44100Hz. But the
> bitclk is not 64fs anymore but 32fs only (1.41Mhz). Is there any
> implementation details I miss? What does your codec clock config look
> like?
>
Do you mean it only down to 32fs when LRCLK is 44100HZ ?
And when LRCLK is 48000HZ, all is OK ?

> Another small thing:
>
>  CC      sound/soc/pxa/pxa-ssp.o
>  sound/soc/pxa/pxa-ssp.c:186: warning: 'ssp_get_scr' defined but not used
>
> Daniel
>
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