[alsa-devel] ASoC: pxa2xx-i2s
broonie at sirena.org.uk
Wed Jan 21 14:23:14 CET 2009
On Tue, Jan 20, 2009 at 04:24:21PM -0600, Brian Rhodes wrote:
> This method also works, and does not affect the the other stream. The
> difference for me really seems to be that when DREC is set and DRPL is
> cleared when i2s is enabled it will occasionally never start. I cannot
Without checking the datasheet for the chip this looks broadly
reasonable to me.
> recreate the issue by with the original code if I initialize SACR1 to
> set DREC in startup and do not reset it in hw_params. It is possible
> the problem is with the codec. TLV320dac2x.
What is the clock master in your system?
> hours. Nothing in the i2s controller documentation mentions the
> possibility of anything in the hardware disabling replay, so I am
> confused what is happening here.
If chip documentation were always complete and accurate the world would
be a much better place :)
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