[alsa-devel] [PATCH v2] tlv320aic3x: disable ADC/DAC while changing clock
dg at emlix.com
Thu Apr 2 12:45:03 CEST 2009
On 04/02/2009 12:34 PM, Mark Brown wrote:
> On Thu, Apr 02, 2009 at 10:39:12AM +0300, Jarkko Nikula wrote:
>> My two cents: It supports different sampling rates for ADC and DAC but
>> I don't believe there is practical use or HW doing this. In this setup
>> there is separate word clock signal on GPIO1 for ADC.
> Hrm, that's fairly common for hardware - even with shared LRCLK many
> devices will be able to support asymmetric rates providing there are
> enough BCLKs to drive the data. Presumably the only limit in the codec
> itself is going to be that whatever the PLL is set for will be the
It's only the tlv320aic33 that has GPIO pins.
On the other supported devices the datasheet says on register 98:
"Reserved. Write only 0 to these bits"
While we're at it, there are other registers where we are already writing
values != 0 which are not allowed on aic31 and aic32.
Dipl.-Math. Daniel Glöckner, emlix GmbH, http://www.emlix.com
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