[alsa-devel] ASOC: For SND_SOC_DAIFMT_IB_IF what is invert baseed on?
linuxzsc at gmail.com
Mon Oct 27 04:00:24 CET 2008
2008/10/27 Liam Girdwood <lrg at slimlogic.co.uk>:
> On Sun, 2008-10-26 at 00:31 +0800, Richard Zhao wrote:
>> * DAI hardware signal inversions
>> #define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bclk + frm */
>> #define SND_SOC_DAIFMT_NB_IF (1 << 8) /* normal bclk
>> + inv frm */
>> #define SND_SOC_DAIFMT_IB_NF (2 << 8) /* invert bclk
>> + nor frm */
>> #define SND_SOC_DAIFMT_IB_IF (3 << 8) /* invert bclk + frm */
>> What are frame cock and bit clock invert based on? I2S, PCM or some
>> else bus protocols? Or just high level voltage or low level voltage?
> Generic logic levels (high/low voltage) that can apply to I2S and PCM
It's not bus protocol depended.
For frame start, LRCLK normal is 1, invert is 0.
For data valid, BCLK normal is 1, invert is 0
Is that what you meant?
But when wm8350 in i2s mode, it take SND_SOC_DAIFMT_NB_NF as LRCLK is
0 for frame start.
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