[alsa-devel] define confusion
jkacur at gmail.com
Tue Oct 14 15:16:58 CEST 2008
On Tue, Oct 14, 2008 at 2:29 PM, John Kacur <jkacur at gmail.com> wrote:
> On Tue, Oct 14, 2008 at 2:17 PM, Mark Brown <broonie at sirena.org.uk> wrote:
>> On Tue, Oct 14, 2008 at 01:52:20PM +0200, John Kacur wrote:
>>> I want to use an MCLK generated from an ocillator from i2s, so by
>>> definition, that is the master. I thought that the frames are always
>>> generated by the master (or can it be the other way around if you have
>>> a codec device that can capture?) so does this mean, I should choose
>> The clock configuration for the link refers specifically to the device
>> that is generating the clock for that link - it will derive this clock
>> from some other source but the question is what device is driving each
>> of the clock signals on the link. This could be anything on the link
>> for either clock, any restrictions will be a function of the devices
>> used and the way they are connected in your system. All that "master"
>> refers to is the source of the clock.
>> It's not clear from what you write above what applies in your case.
>> I *think* that you mean that you want to derive both frame and bit
>> clocks from a crystal attached to the codec - if that is the case then
>> you want to use SND_SOC_DAIFMT_CBM_CFM. Otherwise, could you please
>> clarify what your system configuration is - which devices do you want to
>> drive which clock signals?
> Ah, thank you for the explanation, now I understand my source of my
> confusion too, the reference to the frame in the define is the frame
> CLOCK! You are correct, all my clocks are external to the codec. Also
> confusing was what the 'B' was for, now I understand that is the bit
Argh, sorry for another note, but I'm still confused after rereading your note.
My situation is that although the codec has an internal clock, I will
not be using it, (because it is not activated in the presense of an
external clock source on the pin) the bit clock and the master clock
are coming from the i2s bus, and I suppose the details of where they
stem from is irrelevant. If they are not irrelevant, then the master
clock is provided to the i2s bus from a crystal. So that means from
the codec's view point that makes everything SND_SOC_DAIFMT_CBS_CFS.
Does that finally sound correct?
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