[alsa-devel] ASOC, master clock direction

Mark Brown broonie at opensource.wolfsonmicro.com
Fri Jul 18 23:23:19 CEST 2008

On Fri, Jul 18, 2008 at 03:44:37PM -0400, Jon Smirl wrote:
> On 7/18/08, Jon Smirl <jonsmirl at gmail.com> wrote:

> >  3) Something Freescale calls cellphone slave but it is more like clock
> >  distribution.

> >  In cellslave mode one i2s port is in normal slave mode. The clock from
> >  this port is used to drive up to three other i2s ports in master mode.


> >  When the clock frequency changes I need to notify the i2s drivers for
> >  the dependent channels. Do we need a third choice,
> >  SND_SOC_CLOCK_SLAVE? Alternatively I can use another clock id value.

Without having looked at how this works in hardware I'd probably
implement this by using a different clock id for the slave ports if I
wanted to use set_sysclk() to configure cell slave mode.  It sounds like
you've got to choose between two sources within the SoC, one being that
clocked in from the external source and the other regular clocks.  From
what you're saying as far as the individual I2S port is concerned it is
the master in both cases.

> 	switch (dir) {
> 		return 0;
> 	default:
> 		if (!(psc_i2s->sicr & MPC52xx_PSC_SICR_CELLSLAVE)) {
> 			/* implement me */
> 			/* compute and set the needed dividers for the internal clock */
> 			return -EINVAL;
> 		}
> 		psc_i2s->sysclk = freq;
> 		return -EINVAL;
> 	}
> }

If you did use a separate clock id then you could set or clear
MPC52xx_PSC_SICR_CELLSLAVE as appropriate here which might be a bit
easier to write.  It depends on what's clearer and what work is needed
to configure the slave mode - I guess there may be other configuration

Having said that the important thing here is that what you do is
sensible and idiomatic for people working on the platform so it may be
that what you've got already is the most expressive thing.  The clock
configuration is done by machine drivers which will obviously be
platform specific.

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