[alsa-devel] Juli - function of specific GPIOs?

Pavel Hofman pavel.hofman at insite.cz
Fri Jan 18 22:41:51 CET 2008

Hi Takashi,

Sorry for distracting you from the constant struggle with HDA.

I would like to provide complete support for the ESI Juli@ card.
Informing the ADC (AK5385) about current sample rate via the dedicated
GPIOs is fairly simple, as well as the monitoring features (DIGOUT, 
DIGIN, ANAIN, MUTE + volume control of the remaining DACs).

However, I do not understand functions of the GPIO_FREQ_XXKHZ and
GPIO_MULTI_XX GPIOs. The card's user manual says the card can detect
incoming SPDIF rate. AK4114 can either read the rate from the input data
in professional format only, or detect it by comparing external clock 
with the input rate. The AK4114 external clock pin does go to the Xilinx 
CPLD. The GPIOs lead to the CPLD too. Do they in some way control the 
CPLD to provide AK4114 with external clock so that AK4114 can provide 
correct input rate data through its registers?

But if so, where would CPLD get the independent clock when ICE1724 is in 
slave mode, clocked by AK4114? True, the PMCLK output is fed to the 
CPLD, but that would be slaved to AK4114 too. I guess the only 
independent clock during the slave mode would have to come directly from 
the 24.576MHz crystal of ICE, but I could not trace any connection to 
the CPLD.

Perhaps the mysterious AV73-1 helps, I could not google-out any 
information on this IC.

The automated detection of incoming rate is important for setting
correct sample rates in codecs when running on external clock.

If resolved, I would add similar functionality to the MI/ODI/O card for
Prodigy192 too.

I am sorry for bothering you, but the GPIOs named constants in juli.c 
suggest you had access to some documentation about the card. My tracing 
and beeping the card ends with the internal CPLD logic.

Thanks a lot for any information or suggestion.

Best regards,

Pavel Hofman.


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