[alsa-devel] [PATCH] asoc tlv320aic33: skip usage of PLL in some cases

[Daniel Mack]

On Fri, Apr 18, 2008 at 01:47:33PM +0300, Jarkko Nikula wrote:
> > Well, the constraint for that condition is that MCLK = 256*WCLK, and the
> > reason why that works for the chip without PLL is that Q=2. I stated
> > that a little better in the attached patch.
> >
> 
> I would rather refer there just "Fsref = CLKDIV_IN / (128*Q)" as the
> condition where PLL can be disabled (or is mandatory where it must be
> disabled?).
> 
> Referring to data sheet page 27 is not good as it's correct only for certain
> version of AIC33 spec and driver supports other AIC3x chips as well :-)

Ok, I agree. I changed that to find an appropriate value for Q
programmatically. Have a look at the attached patch, please. I hope i
finally got it now ;)

Daniel


Subject: [PATCH] asoc tlv320aic33: skip usage of PLL in some cases

Try to find an appropriate value for Q during clock setup in order to
bypass the usage of the PLL in some cases. This saves some entries in
the dividers table.

Signed-off-by: Daniel Mack <daniel at caiaq.de>

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