[alsa-devel] Enabling in-kernel synch for M-Audio boards

John Rigg aldev at sound-man.co.uk
Tue Sep 18 12:40:33 CEST 2007

On Tue, Sep 18, 2007 at 10:07:05AM +0200, Ludovico Verducci wrote:
> John Rigg ha scritto:
> > On Mon, Sep 17, 2007 at 08:44:03PM +0100, John Rigg wrote:
> >   
> >> On Mon, Sep 17, 2007 at 12:22:19PM +0200, Ludovico Verducci wrote:
> >>> I'm developing a complex multichannel audio distribution system where 
> >>> multiple linux boxes will stream audio data over ethernet and then 
> >>> should play audio at sample level resolution synchronization. The boxes 
> >>> clocks are synchronized over ethernet using PTP. 
> >>> I need to keep in synch the audio board's clocks and I can't use an 
> >>> external wordclock nor s/pdif. 
> >>>       
> >> Won't this cause serious clock jitter problems? I don't see how the
> >> PCI bus can deliver precise enough timing, considering how much other
> >> data it has to handle.
> >>     
> I didn't mean to directly drive the audio board's clock over the PCI
> bus. I think this is simply not feasible. But I think that using control
> signals periodically exchanged over PCI between the audio board and the
> kernel could be possible (if the hardware could support a similar
> feature, of course) to skew the board's clock to keep it in synch with a
> software reference.

Ah, I misunderstood what you meant.

> As far as I know the delta family boards drivers support the
> synchronization of up to 4 audio boards over PCI: at the moment I'm
> reverse engineering the hardware trying to understand how this can be
> accomplished.

I'm aware that some Windows users are using several Delta 1010s
without external sync, but I'm not sure how it is done (or how
good it sounds). AFAIK it would require a VCXO so that the frequency 
of the card's clock could be varied by enough to keep it in sync 
(ie. making the clock oscillator part of a phase locked loop). Looking
at the PCI card on the 1010, I can only see standard fixed-frequency 
crystals. The only PLLs appear to be the internal PLL in the S/PDIF
receiver and the 4046 PLL chip for the word clock input signal.


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